The present invention relates generally to semiconductor circuits, and more specifically to CAM cells and high speed and low power sense circuits for content addressable memory.
A content addressable memory (CAM) is a memory having an array of memory cells that can be commanded to compare all or a subset of the “entries” in the array against an input address. Each entry in the CAM array corresponds to the content of the cells in a particular row of the array. Each row of the array is further associated with a respective match line, which is used as a status line for the row. All or a portion of the CAM array may be compared in parallel to determine whether or not the input address matches any of the entries in the portion selected for comparison. If there is a match to an entry, then the match line for the corresponding row is asserted to indicate the match. Otherwise, the match line is de-asserted to indicate a mismatch (which may also be referred to as a “miss”). Typically, any number of match lines may be asserted, depending on the entries in the array and the input address.
In a typical CAM design, the comparison between a bit of the input address and the content of a CAM cell is performed by a comparison circuit included in the cell. The comparison circuits for all cells in each row may then be coupled to the match line for the row. For simplicity, the comparison circuits may be designed such that a wired-OR operation is implemented for the outputs from all comparison circuits coupled to any given match line. In one common design, the output for each comparison circuit is formed by the drain of an N-channel output transistor. This output transistor is turned ON if there is a mismatch between the input address bit and the memory cell content and is turned OFF otherwise. The match line may be pre-charged to a logic high prior to each comparison operation, and would thereafter remains at logic high only if all output transistors for the row are turned OFF, which would be the case if there is a match between all bits of the entry for the row and the input address. Otherwise, if at least one output transistor is turned ON due to a mismatch, then the match line would be pulled low by these transistors. The signal (or voltage) on the match line may thereafter be sensed or detected to determine whether or not there was a match for that row.
The conventional CAM cell and CAM sensing mechanism described above, though simple in design, have several drawbacks that affect performance. First, speed may be limited by the wired-OR design of the match line, if some speed-enhancing techniques are not employed. Each row may include a large number of cells (e.g., possibly 100 or more cells). In this case, if only one bit in the entire row does not match, then only one output transistor will be turned ON and this transistor will need to pull the entire match line low (e.g., from VDD to VSS). A long time (i.e., t=C·VDD2/I, where C is the capacitance of each entire match line and I is the current of each transistor) may then be required to discharge the line, which would then limit the speed at which the CAM array may be operated. Second, excessive power may be consumed by the CAM design described above. Typically, only one row will match the input address, and all other rows will not match. In this case, all but one match line will be pulled to logic low (e.g., to VSS) by the output transistors that are turned ON due to mismatches. The power consumed may then be computed as (M−1)·C·VDD2, where (M−1) is the number of mismatched rows, C is the capacitance of each match line, and VDD is the voltage swing of the match line during discharge.
As can be seen, there is a need for CAM cells and sense circuits that can ameliorate the shortcomings related to speed and power in the conventional design.